Fabrication of integrated circuit gate field effect transistors

ABSTRACT

A LOW COST OPTIMUM PROCESS FOR FABRICATING MONOLITHIC INTEGRATED CIRCUIT INSULATED GATE FIELD EFFECT TRANSISTORS WHICH UTILIZE A REFRACTORY METAL DIFFUSION MASK. AS THE FIRST STEP, THERE IS DEPOSITED ON THE SEMICONDUCTOR SUBSTRATE A THIN LAYER OF GATE INSULATOR, PREFERABLY A LUMINATE OF GROWN SILICON DIOXIDE AND SILICON NITRIDE, AND A THICK PYROLYTICALLY DEPOSITED FIELD OXIDE. AFTER FORMING A SINGLE OPENING DOWN TO THE SILICON NITRIDE FOR SOURCE, GATE, AND DRAIN REGIONS, AND DEPOSITING A THIN FILM OF MOLYBDENUM, SUBSEQUENT PROCESSING IS COMPLETED WITHOUT REMOVING THE INITIALLY DEPOSITED GATE INSULATOR. THIS INCLUDES FORMING DRAIN AND SOURCE OPENING THROUGH THE REFRACTORY METAL FILM AND GATE INSULATOR LAYERS, DEPOSITING AN ACTIVATOR IMPURITY-DOPED GLASS COATING OVER THE ENTIRE PROCESSED SUBSTRATE, AND DIFFUSING THE ACTIVATOR IMPURITY INTO THE SUBSTRATE USING THE PATTERNED MOLYBDENUM FILM AS A DIFFUSION MASK. CONTACT HOLES ARE THEN MADE THROUGH THE GLASS COATING, AND CONTACT METALLIZATIONS ARE APPLIED.

DEFENSIVE PUBLICATION UNITED STATES PATENT OFFICE Published at the request of the applicant or owner in accordance with the Notice of Dec. 16, 1969, 869 0.G. 687. The abstracts of Defensive Publication applications are identified by distinctly numbered series and are arranged chronologically. The heading of each abstract indicates the number of pages of specification, including claims and sheets of drawings contained in the application as originally filed. The files of these applications are available to the public for inspection and reproduction may be purchased for 30 cents a sheet.

Defensive Publication applications have not been examined as to the merits of alleged invention. The Patent Oilice makes no assertion as to the novelty of the disclosed subject matter.

PUBLISHED JUNE 22, 1971 news on N-I'VPE sl WAFER LAVERS or n snow SILICUN moxie: s: on mime: mo

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new SINGLE OPEMNG F0 souncz, GATEJND DRAIN no re SILICUN NJIRIBE LAYER no n REFRACTORY a MUM. We) HUI PM? H UTE, ITC" ovzm ion source Aun DRAIN omen TB ll VAFKR one!" Acnv Ion-com GU55 FILM DIFF E AUIVATUR iwimm/ 1n ram MYPE sonnet mm mm nzcmoozs :rcu carrier HOLE! oEPosu' u: LCDNYAC 9 in cart, 50 EJND mum A low cost optimum process for fabricating monolithic integrated circuit insulated gate field effect transistors which utilize a refractory metal diffusion mask. As the first step, there is deposited on the semiconductor substrate a thin layer of gate insulator, preferably a laminate of grown silicon dioxide and silicon nitride, and a thick pyrolytically deposited field oxide. After forming a single opening down to the silicon nitride for source, gate, and drain regions, and depositing a thin film of molybdenum, subsequent processing is completed without removing the initially deposited gate insulator. This includes forming drain and source openings through the refractory metal film and gate insulator layers, depositing an activator impurity-doped glass coating over the entire processed substrate, and dilfusing the activator impurity into the substrate using the patterned molybdenum film as a diifusion mask. Contact holes are then made through the glass coating, and contact metallizations are applied.

June 22, IN

G. S. RODARI FABRICATION OF INTEGRATED CIRCUIT GATE FIELD EFFECT TRANSISTORS Filed March 17, 1970 DEPOSIT ON N-TYPE Si WAFER LAYERS OF THIN GROWN SILICON DIOXIDE, SILICON NITRIDE AND THICK FIELD SILICON DIOXIDE ETCH SINGLE OPENING FOR SOURCE, GATE, AND DRAIN DOWN TO SILICON NITRIDE LAYER DEPOSIT REFRACTORY METAL (M0) FILM PATTERN GATE, ETCH OPENINGS FOR SOURCE AND DRAIN DOWN TO Si WAFER DEPOSIT ACTlVATOR-DOPED GLASS FILM, DIFFUSE ACTIVATOR IMPURITY TO FORM P-TYPE SOURCE AND DRAIN ELECTRODES ETCH CONTACT HOLES; DEPOSIT METAL CONTACTS TO GATE, SOURCE, AND DRAIN 2 Sheets-Sheet 1 (fig 2a) (fig 219) (fig 20) (fig .20)

(fig 2a) //I/ I/E/I/ TOR.- v G/A/VP/ERO s. RODA/W,

June 22, 1971 RODAR] FABRICATION OF INTEGRATED CIRCUIT GATE FIELD EFFECT TRANSISTORS Filed March 17, 1970 2 Sheets-Sheet a lA/ VE/V TOR: 6/4 IVP/ERO s. Rom/w, 

